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p roduct s pecification integrated circuits group LH28F800BJHE-PTTLT6 flash memory 8mbit (512kbitx16 / 1mbitx8) (model number: lhf80jt6) spec. issue date: october 26, 2004 spec no: el16192

lhf80jt6 rev. 1.27 handle this document carefully for it contains material protected by international copyright law. any reproduction, full or in part, of this material is prohibited without the express written permission of the company. when using the products covered herein, please observe the conditions written herein and the precautions outlined in the following paragraphs. in no event shall the company be liable for any damages resulting from failure to strictly adhere to these conditions and precautions. (1) the products covered herein are designed and manufactured for the following application areas. when using the products covered herein for the equipment listed in paragraph (2), even for the following application areas, be sure to observe the precautions given in paragraph (2). never use the products for the equipment listed in paragraph (3). ? office electronics ? instrumentation and measuring equipment ? machine tools ? audiovisual equipment ? home appliance ? communication equipment other than for trunk lines (2) those contemplating using the products covered herein for the following equipment which demands high reliability , should first contact a sales representative of the company and then accept responsibility for incorporating into the design fail-safe operation, redundancy, and other appropriate measures for ensuring reliability and safety of the equipment and the overall system. ? control and safety devices for airplanes, trains, automobiles, and other transportation equipment ? mainframe computers ? traffic control systems ? gas leak detectors and automatic cutoff devices ? rescue and security equipment ? other safety devices and safety equipment, etc. (3) do not use the products covered herein for the following equipment which demands extremely high performance in terms of functionality, reliability, or accuracy. ? aerospace equipment ? communications equipment for trunk lines ? control equipment for the nuclear power industry ? medical equipment related to life support, etc. (4) please direct all queries and comments regarding the interpretation of the above three paragraphs to a sales representative of the company. please direct all queries regarding the products covered herein to a sales representative of the company.
lhf80jt6 1 rev. 1.27 contents page 1 introduction .............................................................. 3 1.1 features ........................................................................ 3 1.2 product overview ......................................................... 3 1.3 product description ...................................................... 4 1.3.1 package pinout ....................................................... 4 1.3.2 block organization................................................. 4 2 principles of operation........................................ 7 2.1 data protection ............................................................. 8 3 bus operation ............................................................ 8 3.1 read.............................................................................. 8 3.2 output disable .............................................................. 8 3.3 standby ......................................................................... 8 3.4 reset............................................................................. 8 3.5 read identifier codes................................................... 9 3.6 otp(one time program) block .................................. 9 3.7 write ........................................................................... 10 4 command definitions ........................................... 10 4.1 read array command................................................ 12 4.2 read identifier codes command ............................... 12 4.3 read status register command ................................. 12 4.4 clear status register command................................. 12 4.5 block erase command............................................... 13 4.6 full chip erase command ......................................... 13 4.7 word/byte write command....................................... 13 4.8 block erase suspend command ................................ 14 4.9 word/byte write suspend command ........................ 14 4.10 set block and permanent lock-bit commands ....... 15 4.11 clear block lock-bits command ............................ 15 4.12 otp program command .......................................... 16 4.13 block locking by the wp# ...................................... 16 page 5 design considerations ....................................... 27 5.1 three-line output control ........................................ 27 5.2 ry/by# and wsm polling ....................................... 27 5.3 power supply decoupling ......................................... 27 5.4 v ccw trace on printed circuit boards ..................... 27 5.5 v cc , v ccw , rp# transitions .................................... 27 5.6 power-up/do wn protecti on....................................... 28 5.7 power dissipation ...................................................... 28 5.8 data protection method ............................................. 28 6 electrical specifications ................................ 29 6.1 absolute maximum ratings ...................................... 29 6.2 operating conditions ................................................. 29 6.2.1 capacitance .......................................................... 29 6.2.2 ac input/output test conditions ........................ 30 6.2.3 dc characteristics ............................................... 31 6.2.4 ac characteristics - read-only operations ........ 33 6.2.5 ac characteristics - write operations ................ 36 6.2.6 alternative ce#-controlled writes...................... 38 6.2.7 reset operations .................................................. 40 6.2.8 block erase, full chip erase, word/byte write and lock-bit configuration performance ................. 41 7 package and packing specification............ 42
lhf80jt6 2 rev. 1.27 LH28F800BJHE-PTTLT6 8m-bit ( 512kbit 16 / 1mbit 8 ) boot block flash memory low voltage operation v cc =v ccw =2.7v-3.6v single voltage otp(one time program) block 3963 word + 4 word program only array user-configurable 8 or 16 operation high-performance read access time 90ns(v cc =2.7v-3.6v) operating temperature -40c to +85c low power management typ. 2a (v cc =3.0v) standby current automatic power savings mode decreases i ccr in static mode typ. 120a (v cc =3.0v, t a =+25c, f=32khz) read current optimized array blocking architecture two 4k-word (8k-byte) boot blocks six 4k-word (8k-byte) parameter blocks fifteen 32k-word (64k-byte) main blocks top boot location extended cycling capability minimum 100,000 block erase cycles enhanced automated suspend options word/byte write suspend to read block erase suspend to word/byte write block erase suspend to read enhanced data protection features absolute protection with v ccw v ccwlk block erase, full chip erase, word/byte write and lock-bit configuration lockout during power transitions block locking with command and wp# permanent locking automated block erase, full chip erase, word/byte write and lock-bit configuration command user interface (cui) status register (sr) sram-compatible write interface industry-standard packaging 48-lead tsop etox tm* nonvolatile flash technology cmos process (p-type silicon substrate) not designed or rated as radiation hardened the product is a high-density, low-cost, nonvolatile, read/write storage solution for a wide range of applications. the product can operate at v cc =2.7v-3.6v and v ccw =2.7v-3.6v or 11.7v-12.3v. its low voltage operation capability realize battery life and suits for cellular phone application. its boot, parameter and main-blocked architecture, low voltage and extended cycling provide for highly flexible component suitable for portable terminals and personal computers. its enhanced suspend capabilities provide for an ideal solution for cod e + data storage applications. for secure code storage applications, such as networking, where code is either directly executed out of flash or downloaded to dram, the product offers four levels of protection: absolute protection with v ccw v ccwlk , selective hardware block locking or flexible software block locking. these alternatives give designers ultimate control of their code security needs. the product is manufactured on sharp?s 0.25m etox tm* process technology. it come in industry-standard package: the 48-lead tsop, ideal for board constrained applications. *etox is a trademark of intel corporation.
lhf80jt6 3 rev. 1.27 1 introduction this datasheet contains the product specifications. section 1 provides a flash memory overview. sections 2, 3, 4 and 5 describe the memory organization and functionality. section 6 covers electrical specifications. 1.1 features key enhancements of the product are: ? single low voltage operation ? low power consumption ? enhanced suspend capabilities ? boot block architecture please note following: ? v ccwlk has been lowered to 1.0v to support 2.7v- 3.6v block erase, full chip erase, word/byte write and lock-bit configuration operations. the v ccw voltage transitions to gnd is recommended for designs that switch v ccw off during read operation. 1.2 product overview the product is a high-performance 8m-bit boot block flash memory organized as 512k-word of 16 bits or 1m- byte of 8 bits. the 512k-word/1m-byte of data is arranged in two 4k-word/8k-byte boot blocks, six 4k-word/8k- byte parameter blocks and fifteen 32k-word/64k-byte main blocks which are individually erasable, lockable and unlockable in-system. the memory map is shown in figure 3. the dedicated v ccw pin gives complete data protection when v ccw v ccwlk . a command user interface (cui) serves as the interface between the system processor and internal operation of the device. a valid command sequence written to the cui initiates device automation. an internal write state machine (wsm) automatically executes the algorithms and timings necessary for block erase, full chip erase, word/byte write and lock-bit configuration operations. a block erase operation erases one of the device?s 32k- word/64k-byte blocks typically within 1.2s (3v v cc , 3v v ccw ), 4k-word/8k-byte blocks typically within 0.6s (3v v cc , 3v v ccw ) independent of other blocks. each block can be independently erased minimum 100,000 times. block erase suspend mode allows system software to suspend block erase to read or write data from any other block. writing memory data is performed in word/byte increments of the device?s 32k-word blocks typically within 33s (3v v cc , 3v v ccw ), 64k-byte blocks typically within 31s (3v v cc , 3v v ccw ), 4k-word blocks typically within 36s (3v v cc , 3v v ccw ), 8k- byte blocks typically within 32s (3v v cc , 3v v ccw ). word/byte write suspend mode enables the system to read data or execute code from any other flash memory array location. individual block locking uses a combination of bits, thirty- nine block lock-bits, a permanent lock-bit and wp# pin, to lock and unlock blocks. block lock-bits gate block erase, full chip erase and word/byte write operations, while the permanent lock-bit gates block lock-bit modification and locked block alternation. lock-bit configuration operations (set block lock-bit, set permanent lock-bit and clear block lock-bits commands) set and cleared lock-bits. the status register indicates when the wsm?s block erase, full chip erase, word/byte write or lock-bit configuration operation is finished. the ry/by# output gives an additional indicator of wsm activity by providing both a hardware signal of status (versus software polling) and status masking (interrupt masking for background block erase, for example). status polling using ry/by# minimizes both cpu overhead and system power consumption. when low, ry/by# indicates that the wsm is performing a block erase, full chip erase, word/byte write or lock-bit configuration. ry/by#-high z indicates that the wsm is ready for a new command, block erase is suspended (and word/byte write is inactive), word/byte write is suspended, or the device is in reset mode.
lhf80jt6 4 rev. 1.27 the access time is 90ns (t avqv ) over the operating temperature range (-40c to +85c) and v cc supply voltage range of 2.7v-3.6v. the automatic power savings (aps) feature substantially reduces active current when the device is in static mode (addresses not switching). in aps mode, the typical i ccr current is 2a (cmos) at 3.0v v cc . when ce# and rp# pins are at v cc , the i cc cmos standby mode is enabled. when the rp# pin is at gnd, reset mode is enabled which minimizes power consumption and provides write protection. a reset time (t phqv ) is required from rp# switching high until outputs are valid. likewise, the device has a wake time (t phel ) from rp#-high until writes to the cui are recognized. with rp# at gnd, the wsm is reset and the status register is cleared. please do not execute reprogramming "0" for the bit which has already been programed "0". overwrite operation may generate unerasable bit. in case of reprogramming "0" to the data which has been programed "1". program "0" for the bit in which you want to change data from "1" to "0". program "1" for the bit which has already been programmed "0". for example, changing data from "10111101" to "10111100" requires "11111110" programming. 1.3 product description 1.3.1 package pinout the product is available in 48-lead tsop package (see figure 2). 1.3.2 block organization this product features an asymmetrically-blocked architecture providing system memory integration. each erase block can be erased independently of the others up to 100,000 times. for the address locations of the blocks, see the memory map in figure 3. boot blocks: the boot block is intended to replace a dedicated boot prom in a microprocessor or microcontroller-based system. this boot block 4k words (4,096words) features hardware controllable write- protection to protect the crucial microprocessor boot code from accidental modification. the protection of the boot block is controlled using a combination of the v ccw , rp#, wp# pins and block lock-bit. parameter blocks: the boot block architecture includes parameter blocks to facilitate storage of frequently update small parameters that would normally require an eeprom. by using software techniques, the word-rewrite functionality of eeproms can be emulated. each boot block component contains six parameter blocks of 4k words (4,096 words) each. the protection of the parameter block is controlled using a combination of the v ccw , rp# and block lock-bit. main blocks: the reminder is divided into main blocks for data or code storage. each 8m-bit device contains fifteen 32k words (32,768 words) blocks. the protection of the main block is controlled using a combination of the v ccw , rp# and block lock-bit.
output buffer input buffer input buffer y decoder identifier register output multiplexer status register data comparator y-gating data register command user interface i/o logic write state machine program/erase voltage switch v cc byte# ce# we# oe# rp# ry/by# v ccw v cc gnd x decoder address latch address counter main block 0 main block 1 main block 14 otp block 32k-word (64k-byte) main blocks 15 boot block 0 boot block 1 parameter block 0 parameter block 1 parameter block 2 parameter block 3 parameter block 4 parameter block 5 a -1 -a 18 dq 0 -dq 15 wp# main block 13 48-lead tsop standard pinout 12mm x 20mm top view a 18 a 17 a 16 a 15 a 14 a 13 a 12 ce# v ccw rp# a 11 a 10 a 9 a 8 a 7 a 6 a 5 a 4 nc ry/by# we# oe# dq 7 dq 6 dq 5 dq 4 v cc gnd gnd dq 3 dq 2 dq 1 dq 0 a 0 a 1 a 2 a 3 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 46 44 42 43 47 48 45 21 22 23 24 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 19 20 18 dq 14 dq 13 dq 15 /a -1 dq 12 dq 8 dq 9 dq 11 dq 10 wp# byte# nc lhf80jt6 5 rev. 1.27 figure 1. block diagram figure 2. tsop 48-lead pinout
lhf80jt6 6 rev. 1.27 table 1. pin descriptions symbol type name and function a -1 a 0 -a 18 input address inputs: inputs for addresses during read and write operations. addresses are internally latched during a write cycle. a -1 : lower address input while byte# is v il . a -1 pin changes dq 15 pin while byte# is v ih . a 15 -a 18 : main block address. a 12 -a 18 : boot and parameter block address. dq 0 -dq 15 input/ output data input/outputs: inputs data and commands during cui write cycles; outputs data during memory array, status register and identifier code read cycles. data pins float to high- impedance when the chip is deselected or outputs are disabled. data is internally latched during a write cycle. dq 8 -dq 15 pins are not used while byte mode (byte#=v il ). then, dq 15 pin changes a -1 address input. ce# input chip enable: activates the device?s control logic, input buffers, decoders and sense amplifiers. ce#-high deselects the device and reduces power consumption to standby levels. rp# input reset: resets the device internal automation. rp#-high enables normal operation. when driven low, rp# inhibits write operations which provides data protection during power transitions. exit from reset mode sets the device to read array mode. rp# must be v il during power-up. oe# input output enable: gates the device?s outputs during a read cycle. we# input write enable: controls writes to the cui and array blocks. addresses and data are latched on the rising edge of the we# pulse. wp# input write protect: when wp# is v il , boot blocks cannot be written or erased. when wp# is v ih , locked boot blocks can not be written or erased. wp# is not affected parameter and main blocks. byte# input byte enable: byte# v il places device in byte mode (8). all data is then input or output on dq 0-7 , and dq 8-15 float. byte# v ih places the device in word mode (16), and turns off the a -1 input buffer. ry/by# open drain output ready/busy#: indicates the status of the internal wsm. when low, the wsm is performing an internal operation (block erase, full chip erase, word/byte write or lock-bit configuration). ry/by#-high z indicates that the wsm is ready for new commands, block erase is suspended, and word/byte write is inactive, word/byte write is suspended, or the device is in reset mode. v ccw supply block erase, full chip erase, word/byte write or lock-bit configuration power supply: for erasing array blocks, writing words/bytes or configuring lock-bits. with v ccw v ccwlk , memory contents cannot be altered. block erase, full chip erase, word/byte write and lock-bit configuration with an invalid v ccw (see 6.2.3 dc characteristics) produce spurious results and should not be attempted. applying 12v0.3v to v ccw during erase/write can only be done for a maximum of 1000 cycles on each block. v ccw may be connected to 12v0.3v for a total of 80 hours maximum. v cc supply device power supply: do not float any power pins. with v cc v lko , all write attempts to the flash memory are inhibited. device operations at invalid v cc voltage (see 6.2.3 dc characteristics) produce spurious results and should not be attempted. gnd supply ground: do not float any ground pins. nc no connect: lead is not internal connected; it may be driven or floated.
top boot 32kw/64kb main block 14 32kw/64kb main block 13 32kw/64kb main block 12 32kw/64kb main block 11 32kw/64kb main block 10 32kw/64kb main block 9 32kw/64kb main block 8 32kw/64kb main block 7 32kw/64kb main block 6 32kw/64kb main block 5 32kw/64kb main block 4 32kw/64kb main block 3 32kw/64kb main block 2 32kw/64kb main block 1 32kw/64kb main block 0 4kw/8kb boot block 0 4kw/8kb boot block 1 4kw/8kb parameter block 0 4kw/8kb parameter block 1 4kw/8kb parameter block 2 4kw/8kb parameter block 3 4kw/8kb parameter block 4 4kw/8kb parameter block 5 7ffff 7f000 7efff 7e000 7dfff 7d000 7cfff 7c000 7bfff 7b000 7afff 7a000 79fff 79000 78fff 78000 58000 5ffff 70000 68000 6ffff 60000 67fff 30000 37fff 50000 57fff 48000 4ffff 40000 47fff 38000 3ffff 08000 0ffff 28000 2ffff 20000 27fff 18000 1ffff 10000 17fff 00000 07fff 77fff [a 18 -a 0 ] [a 18 -a -1 ] fffff fe000 fdfff fc000 fbfff fa000 f9fff f8000 f7fff f6000 f5fff f4000 f3fff f2000 f1fff f0000 b0000 bffff e0000 d0000 dffff c0000 cffff 60000 6ffff a0000 affff 90000 9ffff 80000 8ffff 70000 7ffff 10000 1ffff 50000 5ffff 40000 4ffff 30000 3ffff 20000 2ffff 00000 0ffff effff lhf80jt6 7 rev. 1.27 2 principles of operation the product includes an on-chip wsm to manage block erase, full chip erase, word/byte write and lock-bit configuration functions. it allows for: fixed power supplies during block erase, full chip erase, word/byte write and lock-bit configuration, and minimal processor overhead with ram-like interface timings. after initial device power-up or return from reset mode (see section 3 bus operations), the device defaults to read array mode. manipulation of external memory control pins allow array read, standby and output disable operations. status register and identifier codes can be accessed through the cui independent of the v ccw voltage. high voltage on v ccw enables successful block erase, full chip erase, word/byte write and lock-bit configurations. all functions associated with altering memory contents?block erase, full chip erase, word/byte write, lock-bit configuration, status and identifier codes?are accessed via the cui and verified through the status register. commands are written using standard microprocessor write timings. the cui contents serve as input to the wsm, which controls the block erase, full chip erase, word/byte write and lock-bit configuration. the internal algorithms are regulated by the wsm, including pulse repetition, internal verification and margining of data. addresses and data are internally latched during write cycles. writing the appropriate command outputs array data, accesses the identifier codes or outputs status register data. interface software that initiates and polls progress of block erase, full chip erase, word/byte write and lock-bit configuration can be stored in any block. this code is copied to and executed from system ram during flash memory updates. after successful completion, reads are again possible via the read array command. block erase suspend allows system software to suspend a block erase to read/write data from/to blocks other than that which is suspend. word/byte write suspend allows system software to suspend a word/byte write to read data from any other flash memory array location. figure 3. memory map
lhf80jt6 8 rev. 1.27 2.1 data protection when v ccw v ccwlk , memory contents cannot be altered. the cui, with two-step block erase, full chip erase, word/byte write or lock-bit configuration command sequences, provides protection from unwanted operations even when high voltage is applied to v ccw . all write functions are disabled when v cc is below the write lockout voltage v lko or when rp# is at v il . the device?s block locking capability provides additional protection from inadvertent code or data alteration by gating block erase, full chip erase and word/byte write operations. refer to table 5 for write protection alternatives. 3 bus operation the local cpu reads and writes flash memory in-system. all bus cycles to or from the flash memory conform to standard microprocessor bus cycles. 3.1 read information can be read from any block, identifier codes or status register independent of the v ccw voltage. rp# can be at v ih . the first task is to write the appropriate read mode command (read array, read identifier codes or read status register) to the cui. upon initial device power-up or after exit from reset mode, the device automatically resets to read array mode. six control pins dictate the data flow in and out of the component: ce#, oe#, byte#, we#, rp# and wp#. ce# and oe# must be driven active to obtain data at the outputs. ce# is the device selection control, and when active enables the selected memory device. oe# is the data output (dq 0 -dq 15 ) control and when active drives the selected memory data onto the i/o bus. byte# is the device i/o interface mode control. we# must be at v ih , rp# must be at v ih , and byte# and wp# must be at v il or v ih . figure 16, 17 illustrates read cycle. 3.2 output disable with oe# at a logic-high level (v ih ), the device outputs are disabled. output pins (dq 0 -dq 15 ) are placed in a high-impedance state. 3.3 standby ce# at a logic-high level (v ih ) places the device in standby mode which substantially reduces device power consumption. dq 0 -dq 15 outputs are placed in a high- impedance state independent of oe#. if deselected during block erase, full chip erase, word/byte write or lock-bit configuration, the device continues functioning, and consuming active power until the operation completes. 3.4 reset rp# at v il initiates the reset mode. in read modes, rp#-low deselects the memory, places output drivers in a high-impedance state and turns off all internal circuits. rp# must be held low for a minimum of 100ns. time t phqv is required after return from reset mode until initial memory access outputs are valid. after this wake-up interval, normal operation is restored. the cui is reset to read array mode and status register is set to 80h. during block erase, full chip erase, word/byte write or lock-bit configuration modes, rp#-low will abort the operation. ry/by# remains low until the reset operation is complete. memory contents being altered are no longer valid; the data may be partially erased or written. time t phwl is required after rp# goes to logic-high (v ih ) before another command can be written. as with any automated device, it is important to assert rp# during system reset. when the system comes out of reset, it expects to read from the flash memory. automated flash memories provide status information when accessed during block erase, full chip erase, word/byte write or lock-bit configuration modes. if a cpu reset occurs with no flash memory reset, proper cpu initialization may not occur because the flash memory may be providing status information instead of array data. sharp?s flash memories allow proper cpu initialization following a system reset through the use of the rp# input. in this application, rp# is controlled by the same reset# signal that resets the system cpu.
(parameter blocks 1 through 4) 7cfff 79000 [a 18 -a 0 ] 7efff 7e002 7e001 7e000 boot block 1 reserved for future implementation reserved for future implementation boot block 1 lock configuration code 7e003 78fff 78002 78001 78000 78003 parameter block 5 reserved for future implementation reserved for future implementation parameter block 5 lock configuration code 7dfff 7d002 7d001 7d000 7d003 parameter block 0 reserved for future implementation reserved for future implementation parameter block 0 lock configuration code (main blocks 1 through 13) 6ffff 08000 77fff 70002 70001 70000 70003 main block 0 reserved for future implementation reserved for future implementation main block 0 lock configuration code top boot 7ffff 7f002 7f001 7f000 boot block 0 reserved for future implementation reserved for future implementation boot block 0 lock configuration code 7f003 07fff 00004 00002 00000 device code manufacturer code main block 14 main block 14 lock configuration code reserved for future implementation 00003 00001 permanent lock configuration code otp block 0007f 00080 reserved for future implementation 00fff 01000 f9fff f2000 [a 18 -a -1 ] fdfff fc004 fc003 fc000 fc006 f1fff f0004 f0003 f0000 f0006 fbfff fa004 fa003 fa000 fa006 dffff 10000 effff e0004 e0003 e0000 e0006 fffff fe004 fe003 fe000 fe006 0ffff 00008 00004 00000 00006 00002 000ff 00100 01fff 02000 00005 00001 00007 00003 e0005 f0005 fa005 fc005 fe005 customer program area 00085 00fff [a 18 -a 0 ] factory program area otp lock 00081 00080 00084 customer program area lock(bit 1) factory program area lock(bit 0) 0010a 01fff 00102 00100 00109 [a 18 -a -1 ] lhf80jt6 9 rev. 1.27 3.5 read identifier codes the read identifier codes operation outputs the manufacturer code, device code, block lock configuration codes for each block and the permanent lock configuration code (see figure 4). using the manufacturer and device codes, the system cpu can automatically match the device with its proper algorithms. the block lock and permanent lock configuration codes identify locked and unlocked blocks and permanent lock-bit setting. figure 4. device identifier code memory map 3.6 otp(one time program) block the otp block is a special block that can not be erased. the block is divided into two parts. one is a factory program area where a unique number can be written according to customer requirements in sharp factory. this factory program area is "read only" (already locked). the other is a customer program area that can be used by customers. this customer program area can be locked. after locking, this customer program area is protected permanently. the otp block is read in configuration read mode by writing read identifier codes command(90h). to return to read array mode, write read array command(ffh). the otp block is programmed by writing otp program command(c0h). first write otp program command and then write data with address to the device (see figure 5). if otp program is failed, sr.4(word/byte write and set lock-bit status) bit is set to "1". and if this otp block is locked, sr.1(device protect status) bit is set to "1" too. the otp block is also locked by writing otp program command(c0h). first write otp program command and then write data "fffdh" with address "80h" to the device. address "80h" of otp block is otp lock information. bit 0 of address "80h" means factory program area lock status("1" is "not locked", "0" is "locked"). bit 1 of address "80h" means customer program area lock status. the otp lock information can not be cleared, after once it is set. figure 5. otp block address map
lhf80jt6 10 rev. 1.27 3.7 write writing commands to the cui enable reading of device data and identifier codes. they also control inspection and clearing of the status register. when v cc =2.7v-3.6v and v ccw =v ccwh1/2 , the cui additionally controls block erase, full chip erase, word/byte write and lock-bit configuration. the block erase command requires appropriate command data and an address within the block to be erased. the full chip erase command requires appropriate command data and an address within the device. the word/byte write command requires the command and address of the location to be written. set permanent and block lock-bit commands require the command and address within the device (permanent lock) or block within the device (block lock) to be locked. the clear block lock-bits command requires the command and address within the device. the cui does not occupy an addressable memory location. it is written when we# and ce# are active. the address and data needed to execute a command are latched on the rising edge of we# or ce# (whichever goes high first). standard microprocessor write timings are used. figures 18 and 19 illustrate we# and ce# controlled write operations. 4 command definitions when the v ccw voltage v ccwlk , read operations from the status register, identifier codes, or blocks are enabled. placing v ccwh1/2 on v ccw enables successful block erase, full chip erase, word/byte write and lock-bit configuration operations. device operations are selected by writing specific commands into the cui. table 3 defines these commands. table 2.1. bus operations (byte#=v ih ) (1,2) mode notes rp# ce# oe# we# address v ccw dq 0-15 ry/by# (3) read 8 v ih v il v il v ih x x d out x output disable v ih v il v ih v ih x x high z x standby v ih v ih x x x x high z x reset 4 v il x x x x x high z high z read identifier codes 8 v ih v il v il v ih see figure 4, 5 x note 5 high z write 6,7,8 v ih v il v ih v il x x d in x table 2.2. bus operations (byte#=v il ) (1,2) mode notes rp# ce# oe# we# address v ccw dq 0-7 ry/by# (3) read 8 v ih v il v il v ih x x d out x output disable v ih v il v ih v ih x x high z x standby v ih v ih x x x x high z x reset 4 v il x x x x x high z high z read identifier codes 8 v ih v il v il v ih see figure 4, 5 x note 5 high z write 6,7,8 v ih v il v ih v il x x d in x notes: 1. refer to dc characteristics. when v ccw v ccwlk , memory contents can be read, but not altered. 2. x can be v il or v ih for control pins and addresses, and v ccwlk or v ccwh1/2 for v ccw . see dc characteristics for v ccwlk voltages. 3. ry/by# is v ol when the wsm is executing internal block erase, full chip erase, word/byte write or lock-bit configuration algorithms. it is high z during when the wsm is not busy, in block erase suspend mode (with word/byte write inactive), word/byte write suspend mode or reset mode. 4. rp# at gnd0.2v ensures the lowest power consumption. 5. see section 4.2 for read identifier code data. 6. command writes involving block erase, full chip erase, word/byte write or lock-bit configuration are reliably executed when v ccw =v ccwh1/2 and v cc =2.7v-3.6v. 7. refer to table 3 for valid d in during a write operation. 8. never hold oe# low and we# low at the same timing.
lhf80jt6 11 rev. 1.27 table 3. command definitions (10) bus cycles first bus cycle second bus cycle command req?d. notes oper (1) addr (2) data (3) oper (1) addr (2) data (3) read array/reset 1 write x ffh read identifier codes 2 4 write x 90h read ia id read status register 2 write x 70h read x srd clear status register 1 write x 50h block erase 2 5 write x 20h write ba d0h full chip erase 2 write x 30h write x d0h word/byte write 2 5,6 write x 40h or 10h write wa wd block erase and word/byte write suspend 1 5 write x b0h block erase and word/byte write resume 1 5 write x d0h set block lock-bit 2 8 write x 60h write ba 01h clear block lock-bits 2 7,8 write x 60h write x d0h set permanent lock-bit 2 9 write x 60h write x f1h otp program 2 write x c0h write oa od notes: 1. bus operations are defined in table 2.1 and table 2.2. 2. x=any valid address within the device. ia=identifier code address: see figure 4. ba=address within the block being erased or locked. wa=address of memory location to be written. oa=address of otp block to be written: see figure 5. 3. id=data read from identifier codes. srd=data read from status register. see table 6 for a description of the status register bits. wd=data to be written at location wa. data is latched on the rising edge of we# or ce# (whichever goes high first). od=data to be written at location oa. data is latched on the rising edge of we# or ce# (whichever goes high first). 4. following the read identifier codes command, read operations access manufacturer, device, block lock configuration and permanent lock configuration codes. see section 4.2 for read identifier code data. 5. if wp# is v il , boot blocks are locked without block lock-bits state. if wp# is v ih , boot blocks are locked by block lock- bits. the parameter and main blocks are locked by block lock-bits without wp# state. 6. either 40h or 10h are recognized by the wsm as the word/byte write setup. 7. the clear block lock-bits operation simultaneously clears all block lock-bits. 8. if the permanent lock-bit is set, set block lock-bit and clear block lock-bits commands can not be done. 9. once the permanent lock-bit is set, permanent lock-bit reset is unable. 10. commands other than those shown above are reserved by sharp for future device implementations and should not be used.
lhf80jt6 12 rev. 1.27 4.1 read array command upon initial device power-up and after exit from reset mode, the device defaults to read array mode. this operation is also initiated by writing the read array command. the device remains enabled for reads until another command is written. once the internal wsm has started a block erase, full chip erase, word/byte write or lock-bit configuration the device will not recognize the read array command until the wsm completes its operation unless the wsm is suspended via an erase suspend or word/byte write suspend command. the read array command functions independently of the v ccw voltage and rp# can be v ih . 4.2 read identifier codes command the identifier code operation is initiated by writing the read identifier codes command. following the command write, read cycles from addresses shown in figure 4 retrieve the manufacturer, device, block lock configuration and permanent lock configuration codes (see table 4 for identifier code values). to terminate the operation, write another valid command. like the read array command, the read identifier codes command functions independently of the v ccw voltage and rp# can be v ih . following the read identifier codes command, the following information can be read: table 4. identifier codes code address (2) [a 18 -a 0 ] data (3) [dq 7 -dq 0 ] manufacture code 00000h b0h device code 00001h ech block lock configuration ba (1) +2 ? block is unlocked dq 0 =0 ? block is locked dq 0 =1 ? reserved for future use dq 1-7 permanent lock configuration 00003h ? device is unlocked dq 0 =0 ? device is locked dq 0 =1 ? reserved for future use dq 1-7 note: 1. ba selects the specific block lock configuration code to be read. see figure 4 for the device identifier code memory map. 2. a -1 don?t care in byte mode. 3. dq 15 -dq 8 outputs 00h in word mode. 4.3 read status register command the status register may be read to determine when a block erase, full chip erase, word/byte write or lock-bit configuration is complete and whether the operation completed successfully. it may be read at any time by writing the read status register command. after writing this command, all subsequent read operations output data from the status register until another valid command is written. the status register contents are latched on the falling edge of oe# or ce#, whichever occurs. oe# or ce# must toggle to v ih before further reads to update the status register latch. the read status register command functions independently of the v ccw voltage. rp# can be v ih . 4.4 clear status register command status register bits sr.5, sr.4, sr.3 or sr.1 are set to "1"s by the wsm and can only be reset by the clear status register command. these bits indicate various failure conditions (see table 6). by allowing system software to reset these bits, several operations (such as cumulatively erasing multiple blocks or writing several words/bytes in sequence) may be performed. the status register may be polled to determine if an error occurred during the sequence. to clear the status register, the clear status register command (50h) is written. it functions independently of the applied v ccw voltage. rp# can be v ih . this command is not functional during block erase or word/byte write suspend modes.
lhf80jt6 13 rev. 1.27 4.5 block erase command erase is executed one block at a time and initiated by a two-cycle command. a block erase setup is first written, followed by an block erase confirm. this command sequence requires appropriate sequencing and an address within the block to be erased (erase changes all block data to ffffh/ffh). block preconditioning, erase, and verify are handled internally by the wsm (invisible to the system). after the two-cycle block erase sequence is written, the device automatically outputs status register data when read (see figure 6). the cpu can detect block erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the block erase is complete, status register bit sr.5 should be checked. if a block erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid block erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable block erasure can only occur when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . in the absence of this high voltage, block contents are protected against erasure. if block erase is attempted while v ccw v ccwlk , sr.3 and sr.5 will be set to "1". successful block erase requires for boot blocks that wp# is v ih and the corresponding block lock-bit be cleared. in parameter and main blocks case, it must be cleared the corresponding block lock-bit. if block erase is attempted when the excepting above conditions, sr.1 and sr.5 will be set to "1". 4.6 full chip erase command this command followed by a confirm command erases all of the unlocked blocks. a full chip erase setup (30h) is first written, followed by a full chip erase confirm (d0h). after a confirm command is written, device erases the all unlocked blocks block by block. this command sequence requires appropriate sequencing. block preconditioning, erase and verify are handled internally by the wsm (invisible to the system). after the two-cycle full chip erase sequence is written, the device automatically outputs status register data when read (see figure 7). the cpu can detect full chip erase completion by analyzing the output data of the ry/by# pin or status register bit sr.7. when the full chip erase is complete, status register bit sr.5 should be checked. if erase error is detected, the status register should be cleared before system software attempts corrective actions. the cui remains in read status register mode until a new command is issued. if error is detected on a block during full chip erase operation, wsm stops erasing. full chip erase operation start from lower address block, finish the higher address block. full chip erase can not be suspended. this two-step command sequence of set-up followed by execution ensures that block contents are not accidentally erased. an invalid full chip erase command sequence will result in both status register bits sr.4 and sr.5 being set to "1". also, reliable full chip erasure can only occur when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . in the absence of this high voltage, block contents are protected against erasure. if full chip erase is attempted while v ccw v ccwlk , sr.3 and sr.5 will be set to "1". successful full chip erase requires for boot blocks that wp# is v ih and the corresponding block lock-bit be cleared. in parameter and main blocks case, it must be cleared the corresponding block lock-bit. if all blocks are locked, sr.1 and sr.5 will be set to "1". 4.7 word/byte write command word/byte write is executed by a two-cycle command sequence. word/byte write setup (standard 40h or alternate 10h) is written, followed by a second write that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the word/byte write and write verify algorithms internally. after the word/byte write sequence is written, the device automatically outputs status register data when read (see figure 8). the cpu can detect the completion of the word/byte write event by analyzing the ry/by# pin or status register bit sr.7. when word/byte write is complete, status register bit sr.4 should be checked. if word/byte write error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully write to "0"s. the cui remains in read status register mode until it receives another command. reliable word/byte writes can only occur when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . in the absence of this high voltage, memory contents are protected against word/byte writes. if word/byte write is attempted while v ccw v ccwlk , status register bits sr.3 and sr.4 will be set to "1". successful word/byte write requires for boot blocks that wp# is v ih and the corresponding block lock- bit be cleared. in parameter and main blocks case, it must be cleared the corresponding block lock-bit. if word/byte write is attempted when the excepting above conditions, sr.1 and sr.4 will be set to "1".
lhf80jt6 14 rev. 1.27 4.8 block erase suspend command the block erase suspend command allows block-erase interruption to read or word/byte write data in another block of memory. once the block erase process starts, writing the block erase suspend command requests that the wsm suspend the block erase sequence at a predetermined point in the algorithm. the device outputs status register data when read after the block erase suspend command is written. polling status register bits sr.7 and sr.6 can determine when the block erase operation has been suspended (both will be set to "1"). ry/by# will also transition to high z. specification t whrz2 defines the block erase suspend latency. when block erase suspend command write to the cui, if block erase was finished, the device places read array mode. therefore, after block erase suspend command write to the cui, read status register command (70h) has to write to cui, then status register bit sr.6 should be checked for places the device in suspend mode. at this point, a read array command can be written to read data from blocks other than that which is suspended. a word/byte write command sequence can also be issued during erase suspend to program data in other blocks. using the word/byte write suspend command (see section 4.9), a word/byte write operation can also be suspended. during a word/byte write operation with block erase suspended, status register bit sr.7 will return to "0" and the ry/by# output will transition to v ol . however, sr.6 will remain "1" to indicate block erase suspend status. the only other valid commands while block erase is suspended are read status register and block erase resume. after a block erase resume command is written to the flash memory, the wsm will continue the block erase process. status register bits sr.6 and sr.7 will automatically clear and ry/by# will return to v ol . after the erase resume command is written, the device automatically outputs status register data when read (see figure 9). v ccw must remain at v ccwh1/2 (the same v ccw level used for block erase) while block erase is suspended. rp# must also remain at v ih . wp# must also remain at v il or v ih (the same wp# level used for block erase). block erase cannot resume until word/byte write operations initiated during block erase suspend have completed. if the time between writing the block erase resume command and writing the block erase suspend command is shorter than t eres and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation. 4.9 word/byte write suspend command the word/byte write suspend command allows word/byte write interruption to read data in other flash memory locations. once the word/byte write process starts, writing the word/byte write suspend command requests that the wsm suspend the word/byte write sequence at a predetermined point in the algorithm. the device continues to output status register data when read after the word/byte write suspend command is written. polling status register bits sr.7 and sr.2 can determine when the word/byte write operation has been suspended (both will be set to "1"). ry/by# will also transition to high z. specification t whrz1 defines the word/byte write suspend latency. when word/byte write suspend command write to the cui, if word/byte write was finished, the device places read array mode. therefore, after word/byte write suspend command write to the cui, read status register command (70h) has to write to cui, then status register bit sr.2 should be checked for places the device in suspend mode. at this point, a read array command can be written to read data from locations other than that which is suspended. the only other valid commands while word/byte write is suspended are read status register and word/byte write resume. after word/byte write resume command is written to the flash memory, the wsm will continue the word/byte write process. status register bits sr.2 and sr.7 will automatically clear and ry/by# will return to v ol . after the word/byte write resume command is written, the device automatically outputs status register data when read (see figure 10). v ccw must remain at v ccwh1/2 (the same v ccw level used for word/byte write) while in word/byte write suspend mode. rp# must also remain at v ih . wp# must also remain at v il or v ih (the same wp# level used for word/byte write). if the time between writing the word/byte write resume command and writing the word/byte write suspend command is short and both commands are written repeatedly, a longer time is required than standard word/byte write until the completion of the operation.
lhf80jt6 15 rev. 1.27 4.10 set block and permanent lock-bit commands a flexible block locking and unlocking scheme is enabled via a combination of block lock-bits, a permanent lock-bit and wp# pin. the block lock-bits and wp# pin gates program and erase operations while the permanent lock-bit gates block-lock bit modification. with the permanent lock-bit not set, individual block lock-bits can be set using the set block lock-bit command. the set permanent lock-bit command, sets the permanent lock-bit. after the permanent lock-bit is set, block lock-bits and locked block contents cannot altered. see table 5 for a summary of hardware and software write protection options. set block lock-bit and permanent lock-bit are executed by a two-cycle command sequence. the set block or permanent lock-bit setup along with appropriate block or device address is written followed by either the set block lock-bit confirm (and an address within the block to be locked) or the set permanent lock-bit confirm (and any device address). the wsm then controls the set lock-bit algorithm. after the sequence is written, the device automatically outputs status register data when read (see figure 11). the cpu can detect the completion of the set lock-bit event by analyzing the ry/by# pin output or status register bit sr.7. when the set lock-bit operation is complete, status register bit sr.4 should be checked. if an error is detected, the status register should be cleared. the cui will remain in read status register mode until a new command is issued. this two-step sequence of set-up followed by execution ensures that lock-bits are not accidentally set. an invalid set block or permanent lock-bit command will result in status register bits sr.4 and sr.5 being set to "1". also, reliable operations occur only when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . in the absence of this high voltage, lock-bit contents are protected against alteration. a successful set block lock-bit operation requires that the permanent lock-bit be cleared. if it is attempted with the permanent lock-bit set, sr.1 and sr.4 will be set to "1" and the operation will fail. 4.11 clear block lock-bits command all set block lock-bits are cleared in parallel via the clear block lock-bits command. with the permanent lock-bit not set, block lock-bits can be cleared using only the clear block lock-bits command. if the permanent lock-bit is set, block lock-bits cannot cleared. see table 5 for a summary of hardware and software write protection options. clear block lock-bits operation is executed by a two-cycle command sequence. a clear block lock-bits setup is first written. after the command is written, the device automatically outputs status register data when read (see figure 12). the cpu can detect completion of the clear block lock-bits event by analyzing the ry/by# pin output or status register bit sr.7. when the operation is complete, status register bit sr.5 should be checked. if a clear block lock-bit error is detected, the status register should be cleared. the cui will remain in read status register mode until another command is issued. this two-step sequence of set-up followed by execution ensures that block lock-bits are not accidentally cleared. an invalid clear block lock-bits command sequence will result in status register bits sr.4 and sr.5 being set to "1". also, a reliable clear block lock-bits operation can only occur when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . if a clear block lock-bits operation is attempted while v ccw v ccwlk , sr.3 and sr.5 will be set to "1". in the absence of this high voltage, the block lock-bits content are protected against alteration. a successful clear block lock-bits operation requires that the permanent lock-bit is not set. if it is attempted with the permanent lock-bit set, sr.1 and sr.5 will be set to "1" and the operation will fail. if a clear block lock-bits operation is aborted due to v ccw or v cc transitioning out of valid range or rp# active transition, block lock-bit values are left in an undetermined state. a repeat of clear block lock-bits is required to initialize block lock-bit contents to known values. once the permanent lock-bit is set, it cannot be cleared.
lhf80jt6 16 rev. 1.27 4.12 otp program command otp program is executed by a two-cycle command sequence. otp program command(c0h) is written, followed by a second write cycle that specifies the address and data (latched on the rising edge of we#). the wsm then takes over, controlling the otp program and program verify algorithms internally. after the otp program command sequence is completed, the device automatically outputs status register data when read (see figure 13). the cpu can detect the completion of the otp program by analyzing the output data of the ry/by# pin or status register bit sr.7. when otp program is completed, status register bit sr.4 should be checked. if otp program error is detected, the status register should be cleared. the internal wsm verify only detects errors for "1"s that do not successfully program to "0"s. the cui remains in read status register mode until it receives other commands. reliable otp program can be executed only when v cc =2.7v-3.6v and v ccw =v ccwh1/2 . in the absence of this voltage, memory contents are protected against otp programs. if otp program is attempted while v ccw v ccwlk , status register bits sr.3 and sr.4 is set to "1". if otp write is attempted when the otp lock-bit is set, sr.1 and sr.4 is set to "1". 4.13 block locking by the wp# this boot block flash memory architecture features two hardware-lockable boot blocks so that the kernel code for the system can be kept secure while other blocks are programmed or erased as necessary. the lockable two boot blocks are locked when wp#=v il ; any program or erase operation to a locked block will result in an error, which will be reflected in the status register. for top configuration, the top two boot blocks are lockable. for the bottom configuration, the bottom two boot blocks are lockable. if wp# is v ih and block lock- bit is not set, boot block can be programmed or erased normally (unless v ccw is below v ccwlk ). wp# is valid only two boot blocks, other blocks are not affected.
lhf80jt6 17 rev. 1.27 table 5. write protection alternatives (1) operation v ccw rp# permanent lock-bit block lock-bit wp# effect block erase v ccwlk x x x x all blocks locked. or >v ccwlk v il x x x all blocks locked. word/byte v ih x 0 v il 2 boot blocks locked. write v ih block erase and word/byte write enabled. 1 v il block erase and word/byte write disabled. v ih block erase and word/byte write disabled. full chip v ccwlk x x x x all blocks locked. erase >v ccwlk v il x x x all blocks locked. v ih x x v il all unlocked blocks are erased. 2 boot blocks and locked blocks are not erased. v ih all unlocked blocks are erased, locked blocks are not erased. set block v ccwlk x x x x set block lock-bit disabled. lock-bit >v ccwlk v il x x x set block lock-bit disabled. v ih 0 x x set block lock-bit enabled. 1 x x set block lock-bit disabled. clear block v ccwlk x x x x clear block lock-bits disabled. lock-bits >v ccwlk v il x x x clear block lock-bits disabled. v ih 0 x x clear block lock-bits enabled. 1 x x clear block lock-bits disabled. set v ccwlk x x x x set permanent lock-bit disabled. permanent >v ccwlk v il x x x set permanent lock-bit disabled. lock-bit v ih x x x set permanent lock-bit enabled. note: 1. x can be v il or v ih for rp# and wp#, and "0" or "1" for permanent lock-bit and block lock-bit. see dc characteristics for v ccwlk voltage.
lhf80jt6 18 rev. 1.27 table 6. status register definition wsms bess ecblbs wbwslbs vccws wbwss dps r 76543210 sr.7 = write state machine status (wsms) 1 = ready 0 = busy sr.6 = block erase suspend status (bess) 1 = block erase suspended 0 = block erase in progress/completed sr.5 = erase and clear block lock-bits status (ecblbs) 1 = error in block erase, full chip erase or clear block lock-bits 0 = successful block erase, full chip erase or clear block lock-bits sr.4 = word/byte write and set lock-bit status (wbwslbs) 1 = error in word/byte write or set block/permanent lock-bit 0 = successful word/byte write or set block/permanent lock-bit sr.3 = v ccw status (vccws) 1 = v ccw low detect, operation abort 0 = v ccw ok sr.2 = word/byte write suspend status (wbwss) 1 = word/byte write suspended 0 = word/byte write in progress/completed sr.1 = device protect status (dps) 1 = block lock-bit, permanent lock-bit and/or wp# lock detected, operation abort 0 = unlock sr.0 = reserved for future enhancements (r) notes: check ry/by# or sr.7 to determine block erase, full chip erase, word/byte write or lock-bit configuration completion. sr.6-0 are invalid while sr.7="0". if both sr.5 and sr.4 are "1"s after a block erase, full chip erase or lock-bit configuration attempt, an improper command sequence was entered. sr.3 does not provide a continuous indication of v ccw level. the wsm interrogates and indicates the v ccw level only after block erase, full chip erase, word/byte write or lock-bit configuration command sequences. sr.3 is not guaranteed to reports accurate feedback only when v ccw v ccwh1/2 . sr.1 does not provide a continuous indication of permanent and block lock-bit and wp# values. the wsm interrogates the permanent lock-bit, block lock-bit and wp# only after block erase, full chip erase, word/byte write or lock-bit configuration command sequences. it informs the system, depending on the attempted operation, if the block lock-bit is set, permanent lock-bit is set and/or wp# is v il . reading the block lock and permanent lock configuration codes after writing the read identifier codes command indicates permanent and block lock-bit status. sr.0 is reserved for future use and should be masked out when polling the status register.
bus operation command comments write write read standby erase setup erase confirm data=20h addr=x data=d0h addr=within block to be erased status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent block erasures. full status check can be done after each block erase or after a sequence of block erasures. write ffh after the last operation to place device in read array mode. bus operation command comments standby check sr.4,5 both 1=command sequence error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=block erase error standby standby standby check sr.3 1=v ccw error detect check sr.1 1=device protect detect start write 20h write d0h, block address read status register sr.7= 0 1 suspend block erase no yes suspend block erase loop full status check if desired block erase complete full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error device protect error command sequence error block erase error sr.1= 1 0 sr.4,5= sr.5= 1 1 0 0 block erase successful read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy write 70h lhf80jt6 19 rev. 1.27 figure 6. automated block erase flowchart
bus operation command comments write write read standby full chip erase confirm data=30h addr=x data=d0h addr=x status register data check sr.7 1=wsm ready 0=wsm busy full status check can be done after each full chip erase. write ffh after the last operation to place device in read array mode. bus operation command comments standby check sr.4,5 both 1=command sequence error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple blocks are erased before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=full chip erase error standby standby check sr.3 1=v ccw error detect full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error command sequence error full chip erase error sr.4,5= sr.5= 1 1 0 0 full chip erase successful start write 30h write d0h read status register sr.7= 0 1 full status check if desired full chip erase complete write 70h read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy full chip erase setup device protect error sr.1= 1 0 standby check sr.1 1=device protect detect (all blocks are locked) lhf80jt6 20 rev. 1.27 figure 7. automated full chip erase flowchart
bus operation command comments write write read standby setup word/byte write word/byte write data=40h or 10h addr=x data=data to be written addr=location to be written status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent word/byte writes. sr full status check can be done after each word/byte write, or after a sequence of word/byte writes. write ffh after the last word/byte write operation to place device in read array mode. bus operation command comments sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=data write error standby standby standby check sr.3 1=v ccw error detect check sr.1 1=device protect detect start write 40h or 10h write word/byte data and address read status register sr.7= 0 1 suspend word/byte write no yes suspend word/byte write loop full status check if desired word/byte write complete full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error device protect error word/byte write error sr.1= 1 0 sr.4= 1 0 word/byte write successful write 70h read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy lhf80jt6 21 rev. 1.27 figure 8. automated word/byte write flowchart
start write b0h word/byte write loop read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h addr=x status register data addr=x check sr.7 1=wsm ready 0=wsm busy yes sr.6= 0 1 read array data done? block erase resumed read array data block erase completed write ffh write d0h standby write erase suspend erase resume check sr.6 1=block erase suspended 0=block erase completed read or word/byte write ? read word/byte write lhf80jt6 22 rev. 1.27 figure 9. block erase suspend/resume flowchart
start write b0h write ffh read status register sr.7= 0 1 no bus operation command comments write read standby data=b0h addr=x data=d0h addr=x status register data addr=x check sr.7 1=wsm ready 0=wsm busy yes sr.2= 0 1 read array data done reading word/byte write resumed read array data word/byte write completed write ffh write d0h standby write write read word/byte write suspend read array word/byte write resume data=ffh addr=x check sr.2 1=word/byte write suspended 0=word/byte write completed read array locations other than that being written. lhf80jt6 23 rev. 1.27 figure 10. word/byte write suspend/resume flowchart
start write 60h write 01h/f1h, block/device address read status register sr.7= 0 1 full status check if desired set lock-bit complete full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error device protect error command sequence error set lock-bit error sr.1= 1 0 sr.4,5= sr.4= 1 1 0 0 set lock-bit successful bus operation command comments write write read standby data=60h addr=x data=01h(block), f1h(permanent) addr=block address(block), device address(permanent) status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent lock-bit set operations. full status check can be done after each lock-bit set operation or after a sequence of lock-bit set operations. write ffh after the last lock-bit set operation to place device in read array mode. set block/permanent lock-bit setup set block or permanent lock-bit confirm bus operation command comments standby check sr.4,5 both 1=command sequence error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple lock-bits are set before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=set lock-bit error standby standby standby check sr.3 1=v ccw error detect check sr.1 1=device protect detect permanent lock-bit is set (set block lock-bit operation) write 70h read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy lhf80jt6 24 rev. 1.27 figure 11. set block and permanent lock-bit flowchart
start write 60h write d0h read status register sr.7= 0 1 full status check if desired clear block lock-bits complete full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error device protect error command sequence error clear block lock-bits error sr.1= 1 0 sr.4,5= sr.5= 1 1 0 0 clear block lock-bits successful bus operation command comments write write read standby data=60h addr=x data=d0h addr=x status register data check sr.7 1=wsm ready 0=wsm busy write ffh after the clear block lock-bits operation to place device in read array mode. clear block lock-bits setup clear block lock-bits confirm bus operation command comments standby check sr.4,5 both 1=command sequence error sr.5, sr.4, sr.3 and sr.1 are only cleared by the clear status register command. if error is detected, clear the status register before attempting retry or other error recovery. check sr.5 1=clear block lock-bits error standby standby standby check sr.3 1=v ccw error detect check sr.1 1=device protect detect permanent lock-bit is set write 70h read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy lhf80jt6 25 rev. 1.27 figure 12. clear block lock-bits flowchart
bus operation command comments write write read standby setup otp program otp program data=c0h addr=x data=data to be written addr=location to be written status register data check sr.7 1=wsm ready 0=wsm busy repeat for subsequent otp programs. sr full status check can be done after each otp program, or after a sequence of otp programs. write ffh after the last otp program operation to place device in read array mode. bus operation command comments sr.4, sr.3 and sr.1 are only cleared by the clear status register command in cases where multiple locations are written before full status is checked. if error is detected, clear the status register before attempting retry or other error recovery. check sr.4 1=data write error standby standby standby check sr.3 1=v ccw error detect check sr.1 1=device protect detect start write c0h write data and address read status register sr.7= 0 1 full status check if desired otp program complete full status check procedure read status register data(see above) sr.3= 1 0 v ccw range error device protect error otp program error sr.1= 1 0 sr.4= 1 0 otp program successful write 70h read status register sr.7= 0 1 write read read status register data=70h addr=x standby status register data check sr.7 1=wsm ready 0=wsm busy lhf80jt6 26 rev. 1.27 figure 13. automated otp program flowchart
lhf80jt6 27 rev. 1.27 5 design considerations 5.1 three-line output control the device will often be used in large memory arrays. sharp provides three control inputs to accommodate multiple memory connections. three-line control provides for: a. lowest possible memory power dissipation. b. complete assurance that data bus contention will not occur. to use these control inputs efficiently, an address decoder should enable ce# while oe# should be connected to all memory devices and the system?s read# control line. this assures that only selected memory devices have active outputs while deselected memory devices are in standby mode. rp# should be connected to the system powergood signal to prevent unintended writes during system power transitions. powergood should also toggle during system reset. 5.2 ry/by# and wsm polling ry/by# is an open drain output that should be connected to v cc by a pull up resistor to provides a hardware method of detecting block erase, full chip erase, word/byte write and lock-bit configuration completion. it transitions low after block erase, full chip erase, word/byte write or lock- bit configuration commands and returns to v oh (while ry/by# is pull up) when the wsm has finished executing the internal algorithm. ry/by# can be connected to an interrupt input of the system cpu or controller. it is active at all times. ry/by# is also high z when the device is in block erase suspend (with word/byte write inactive), word/byte write suspend or reset modes. 5.3 power supply decoupling flash memory power switching characteristics require careful device decoupling. system designers are interested in three supply current issues; standby current levels, active current levels and transient peaks produced by falling and rising edges of ce# and oe#. transient current magnitudes depend on the device outputs? capacitive and inductive loading. two-line control and proper decoupling capacitor selection will suppress transient voltage peaks. each device should have a 0.1f ceramic capacitor connected between its v cc and gnd and between its v ccw and gnd. these high-frequency, low inductance capacitors should be placed as close as possible to package leads. additionally, for every eight devices, a 4.7f electrolytic capacitor should be placed at the array?s power supply connection between v cc and gnd. the bulk capacitor will overcome voltage slumps caused by pc board trace inductance. 5.4 v ccw trace on printed circuit boards updating flash memories that reside in the target system requires that the printed circuit board designer pay attention to the v ccw power supply trace. the v ccw pin supplies the memory cell current for word/byte writing and block erasing. use similar trace widths and layout considerations given to the v cc power bus. adequate v ccw supply traces and decoupling will decrease v ccw voltage spikes and overshoots. 5.5 v cc , v ccw , rp# transitions block erase, full chip erase, word/byte write and lock-bit configuration are not guaranteed if v ccw falls outside of a valid v ccwh1/2 range, v cc falls outside of a valid 2.7v- 3.6v range, or rp# v ih . if v ccw error is detected, status register bit sr.3 is set to "1" along with sr.4 or sr.5, depending on the attempted operation. if rp# transitions to v il during block erase, full chip erase, word/byte write or lock-bit configuration, ry/by# will remain low until the reset operation is complete. then, the operation will abort and the device will enter reset mode. the aborted operation may leave data partially altered. therefore, the command sequence must be repeated after normal operation is restored. device power-off or rp# transitions to v il clear the status register. the cui latches commands issued by system software and is not altered by v ccw or ce# transitions or wsm actions. its state is read array mode upon power-up, after exit from reset mode or after v cc transitions below v lko .
lhf80jt6 28 rev. 1.27 5.6 power-up/down protection the device is designed to offer protection against accidental block erase, full chip erase, word/byte write or lock-bit configuration during power transitions. upon power-up, the device is indifferent as to which power supply (v ccw or v cc ) powers-up first. internal circuitry resets the cui to read array mode at power-up. a system designer must guard against spurious writes for v cc voltages above v lko when v ccw is active. since both we# and ce# must be low for a command write, driving either to v ih will inhibit writes. the cui?s two- step command sequence architecture provides added level of protection against data alteration. in-system block lock and unlock capability prevents inadvertent data alteration. the device is disabled while rp#=v il regardless of its control inputs state. 5.7 power dissipation when designing portable systems, designers must consider battery power consumption not only during device operation, but also for data retention during system idle time. flash memory?s nonvolatility increases usable battery life because data is retained when system power is removed. 5.8 data protection method noises having a level exceeding the limit specified in the specification may be generated under specific operating conditions on some systems. such noises, when induced onto we# signal or power supply, may be interpreted as false commands, causing undesired memory updating. to protect the data stored in the flash memory against unwanted overwriting, systems operating with the flash memory should have the following write protect designs, as appropriate: 1) protecting data in specific block when a lock bit is set, the corresponding block (includes the 2 boot blocks) is protected against overwriting. by setting a wp# to low, only the 2 boot blocks can be protected against overwriting. by using this feature, the flash memory space can be divided into the program section (locked section) and data section (unlocked section). the permanent lock bit can be used to prevent false block bit setting. for further information on setting/resetting lock-bit, refer to the specification. (see chapter 4.10 and 4.11.) 2) data protection through v ccw when the level of v ccw is lower than v ccwlk (lockout voltage), write operation on the flash memory is disabled. all blocks are locked and the data in the blocks are completely write protected. for the lockout voltage, refer to the specification. (see chapter 6.2.3.) 3) data protection through rp# when the rp# is kept low during read mode, the flash memory will be reset mode, then write protecting all blocks. when the rp# is kept low during power up and power down sequence such as voltage transition, write operation on the flash memory is disabled, write protecting all blocks. for the details of rp# control, refer to the specification. (see chapter 5.6 and 6.2.7.)
lhf80jt6 29 rev. 1.27 6 electrical specifications 6.1 absolute maximum ratings* operating temperature during read, block erase, full chip erase, word/byte write and lock-bit configuration .............-40c to +85c (1) storage temperature during under bias ............................... -40c to +85c during non bias ................................ -65c to +125c voltage on any pin (except v cc and v ccw ) ........... -0.5v to v cc +0.5v (2) v cc supply voltage ................................ -0.2v to +4.6v (2) v ccw supply voltage ......................... -0.2v to +13.0v (2,3) output short circuit current................................ 100ma (4) *warning: stressing the device beyond the "absolute maximum ratings" may cause permanent damage. these are stress ratings only. operation beyond the "operating conditions" is not recommended and extended exposure beyond the "operating conditions" may affect device reliability. notes: 1. operating temperature is for extended temperature product defined by this specification. 2. all specified voltages are with respect to gnd. minimum dc voltage is -0.5v on input/output pins and -0.2v on v cc and v ccw pins. during transitions, this level may undershoot to -2.0v for periods <20ns. maximum dc voltage on input/output pins are v cc +0.5v which, during transitions, may overshoot to v cc +2.0v for periods <20ns. 3. maximum dc voltage on v ccw may overshoot to +13.0v for periods <20ns. applying 12v0.3v to v ccw during erase/write can only be done for a maximum of 1000 cycles on each block. v ccw may be connected to 12v0.3v for a total of 80 hours maximum. 4. output shorted for no more than one second. no more than one output shorted at a time. 6.2 operating conditions temperature and v cc operating conditions symbol parameter min. max. unit test condition t a operating temperature -40 +85 c ambient temperature v cc v cc supply voltage (2.7v-3.6v) 2.7 3.6 v 6.2.1 capacitance (1) t a =+25c, f=1mhz symbol parameter typ. max. unit condition c in input capacitance 7 10 pf v in =0.0v c out output capacitance 9 12 pf v out =0.0v note: 1. sampled, not 100% tested.
ac test inputs are driven at 2.7v for a logic "1" and 0.0v for a logic "0". input timing begins, and output timing ends, at 1.3 5v. input rise and fall times (10% to 90%) <10 ns. 2.7 0.0 input test points output 1.35 1.35 1.3v 1n914 device under test c l out c l includes jig capacitance r l =3.3k ? lhf80jt6 30 rev. 1.27 6.2.2 ac input/output test conditions figure 14. transient input/output reference waveform for v cc =2.7v-3.6v test configuration capacitance loading value test configuration c l (pf) v cc =2.7v-3.6v 50 figure 15. transient equivalent testing load circuit
lhf80jt6 31 rev. 1.27 6.2.3 dc characteristics dc characteristics v cc =2.7v-3.6v test sym. parameter notes typ. max. unit conditions i li input load current 1 0.5 a v cc =v cc max. v in =v cc or gnd i lo output leakage current 1 0.5 a v cc =v cc max. v out =v cc or gnd i ccs v cc standby current 1,3,6 2 15 a cmos level inputs v cc =v cc max. ce#=rp#=v cc 0.2v 0.2 2 ma ttl level inputs v cc =v cc max. ce#=rp#=v ih i ccas v cc auto power-save current 1,5,6 2 15 a cmos level inputs v cc =v cc max. ce#=gnd0.2v i ccd v cc reset power-down current 1 2 15 a rp#=gnd0.2v i out (ry/by#)=0ma i ccr v cc read current 1,6 15 25 ma cmos level inputs v cc =v cc max., ce#=gnd f=5mhz, i out =0ma 30 ma ttl level inputs v cc =v cc max., ce#=gnd f=5mhz, i out =0ma i ccw v cc word/byte write or set lock- 1,7 5 17 ma v ccw =2.7v-3.6v bit current 5 12 ma v ccw =11.7v-12.3v i cce v cc block erase, full chip erase or 1,7 4 17 ma v ccw =2.7v-3.6v clear block lock-bits current 4 12 ma v ccw =11.7v-12.3v i ccws i cces v cc word/byte write or block erase suspend current 1,2 1 6 ma ce#=v ih i ccws v ccw standby or read current 1 2 15 a v ccw v cc i ccwr 10 200 a v ccw >v cc i ccwas v ccw auto power-save current 1,5,6 0.1 5 a cmos level inputs v cc =v cc max. ce#=gnd0.2v i ccwd v ccw reset power-down current 1 0.1 5 a rp#=gnd0.2v i ccww v ccw word/byte write or set lock- 1,7 12 40 ma v ccw =2.7v-3.6v bit current 30 ma v ccw =11.7v-12.3v i ccwe v ccw block erase, full chip erase 1,7 8 25 ma v ccw =2.7v-3.6v or clear block lock-bits current 20 ma v ccw =11.7v-12.3v i ccwws i ccwes v ccw word/byte write or block erase suspend current 1 10 200 a v ccw =v ccwh1/2
lhf80jt6 32 rev. 1.27 dc characteristics (continued) v cc =2.7v-3.6v sym. parameter notes min. max. unit test conditions v il input low voltage 7 -0.5 0.8 v v ih input high voltage 7 2.0 v cc +0.5 v v ol output low voltage 3,7 0.4 v v cc =v cc min. i ol =2.0ma v oh1 output high voltage (ttl) 7 2.4 v v cc =v cc min. i oh =-2.0ma v oh2 output high voltage (cmos) 7 0.85 v cc v v cc =v cc min. i oh =-2.5ma v cc -0.4 v v cc =v cc min. i oh =-100a v ccwlk v ccw lockout during normal operations 4,7 1.0 v v ccwh1 v ccw during block erase, full chip erase, word/byte write or lock-bit configuration operations 2.7 3.6 v v ccwh2 v ccw during block erase, full chip erase, word/byte write or lock-bit configuration operations 8 11.7 12.3 v v lko v cc lockout voltage 2.0 v notes: 1. all currents are in rms unless otherwise noted. typical values at nominal v cc voltage and t a =+25c. 2. i ccws and i cces are specified with the device de-selected. if read or word/byte written while in erase suspend mode, the device?s current draw is the sum of i ccws or i cces and i ccr or i ccw , respectively. 3. includes ry/by#. 4. block erases, full chip erase, word/byte writes and lock-bit configurations are inhibited when v ccw v ccwlk , and not guaranteed in the range between v ccwlk (max.) and v ccwh1 (min.), between v ccwh1 (max.) and v ccwh2 (min.) and above v ccwh2 (max.). 5. the automatic power savings (aps) feature is placed automatically power save mode that addresses not switching more than 300ns while read mode. 6. about all of pin except describe test conditions, cmos level inputs are either v cc 0.2v or gnd0.2v, ttl level inputs are either v il or v ih . 7. sampled, not 100% tested. 8. applying 12v0.3v to v ccw during erase/write can only be done for a maximum of 1000 cycles on each block. v ccw may be connected to 12v0.3v for a total of 80 hours maximum.
lhf80jt6 33 rev. 1.27 6.2.4 ac characteristics - read-only operations (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav read cycle time 90 ns t avqv address to output delay 90 ns t elqv ce# to output delay 2 90 ns t phqv rp# high to output delay 600 ns t glqv oe# to output delay 2 50 ns t elqx ce# to output in low z 3 0 ns t ehqz ce# high to output in high z 3 55 ns t glqx oe# to output in low z 3 0 ns t ghqz oe# high to output in high z 3 20 ns t oh output hold from address, ce# or oe# change, whichever occurs first 3 0 ns t fvqv byte# to output delay 3 90 ns t flqz byte# low to output in high z 3 30 ns t elfv ce# to byte# high or low 3,4 5 ns notes: 1. see ac input/output reference waveform for maximum allowable input slew rate. 2. oe# may be delayed up to t elqv -t glqv after the falling edge of ce# without impact on t elqv . 3. sampled, not 100% tested. 4. if byte# transfer during reading cycle, exist the regulations separately.
addresses(a) ce#(e) oe#(g) we#(w) data(d/q) (dq 0 -dq 15 ) rp#(p) v cc standby device address selection data valid address stable t avav t ehqz t ghqz high z valid output t glqv t elqv t glqx t elqx t avqv t phqv high z t oh v il v oh v ol v ih v ih v ih v ih v ih v il v il v il v il lhf80jt6 34 rev. 1.27 figure 16. ac waveform for read operations
addresses(a) ce#(e) oe#(g) byte#(f) data(d/q) (dq 0 -dq 7 ) standby device address selection data valid address stable t avav t ehqz t ghqz high z data output t glqv t elqv t glqx t elqx t avqv high z v il v oh v ol v ih v ih v ih v ih v il v il v il valid output data(d/q) (dq 8 -dq 15 ) high z high z v oh v ol data output t elfv t fvqv t flqz t oh lhf80jt6 35 rev. 1.27 figure 17. byte# timing waveform
lhf80jt6 36 rev. 1.27 6.2.5 ac characteristics - write operations (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav write cycle time 90 ns t phwl rp# high recovery to we# going low 2 1 s t elwl ce# setup to we# going low 10 ns t wlwh we# pulse width 50 ns t shwh wp#v ih setup to we# going high 2 100 ns t vpwh v ccw setup to we# going high 2 100 ns t avwh address setup to we# going high 3 50 ns t dvwh data setup to we# going high 3 50 ns t whdx data hold from we# high 0 ns t whax address hold from we# high 0 ns t wheh ce# hold from we# high 10 ns t whwl we# pulse width high 30 ns t whrl we# high to ry/by# going low or sr.7 going "0" 100 ns t whgl write recovery before read 0 ns t qvvl v ccw hold from valid srd, ry/by# high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, ry/by# high z 2,4 0 ns t fvwh byte# setup to we# going high 5 50 ns t whfv byte# hold from we# high 5 90 ns notes: 1. read timing characteristics during block erase, full chip erase, word/byte write and lock-bit configuration operations are the same as during read-only operations. refer to ac characteristics for read-only operations. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase, full chip erase, word/byte write or lock-bit configuration. 4. v ccw should be held at v ccwh1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (sr.1/3/4/5=0). 5. if byte# switch during reading cycle, exist the regulations separately.
v il v ih high z ("1") v ih v ih v ih v il v il v il v ol ("0") v il v ih v il v ccwlk v ccwh1/2 v ih v il notes: 1. v cc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) ce#(e) oe#(g) we#(w) data(d/q) rp#(p) v ccw (v) ry/by#(r) (sr.7) } } } } } } 12 3 4 5 6 a in a in t avav t avwh t whax t elwl t wheh t whgl t whwl t whqv1,2,3,4 t wlwh t dvwh t whdx valid srd t phwl t whrl t vpwh t qvvl d in d in high z d in wp#(s) v ih v il t shwh t qvsl v ih v il byte#(f) t fvwh t whfv lhf80jt6 37 rev. 1.27 figure 18. ac waveform for we#-controlled write operations
lhf80jt6 38 rev. 1.27 6.2.6 alternative ce#-controlled writes (1) v cc =2.7v-3.6v, t a =-40c to +85c sym. parameter notes min. max. unit t avav write cycle time 90 ns t phel rp# high recovery to ce# going low 2 1 s t wlel we# setup to ce# going low 0 ns t eleh ce# pulse width 50 ns t sheh wp#v ih setup to ce# going high 2 100 ns t vpeh v ccw setup to ce# going high 2 100 ns t aveh address setup to ce# going high 3 50 ns t dveh data setup to ce# going high 3 50 ns t ehdx data hold from ce# high 0 ns t ehax address hold from ce# high 0 ns t ehwh we# hold from ce# high 0 ns t ehel ce# pulse width high 30 ns t ehrl ce# high to ry/by# going low or sr.7 going "0" 100 ns t ehgl write recovery before read 0 ns t qvvl v ccw hold from valid srd, ry/by# high z 2,4 0 ns t qvsl wp# v ih hold from valid srd, ry/by# high z 2,4 0 ns t fveh byte# setup to ce# going high 5 50 ns t ehfv byte# hold from ce# high 5 90 ns notes: 1. in systems where ce# defines the write pulse width (within a longer we# timing waveform), all setup, hold, and inactive we# times should be measured relative to the ce# waveform. 2. sampled, not 100% tested. 3. refer to table 4 for valid a in and d in for block erase, full chip erase, word/byte write or lock-bit configuration. 4. v ccw should be held at v ccwh1/2 until determination of block erase, full chip erase, word/byte write or lock-bit configuration success (sr.1/3/4/5=0). 5. if byte# switch during reading cycle, exist the regulations separately.
v il v ih high z ("1") v ih v il v ol ("0") v il v ih v il v ccwlk v ccwh1/2 v ih v il notes: 1. v cc power-up and standby. 2. write each setup command. 3. write each confirm command or valid address and data. 4. automated erase or program delay. 5. read status register data. 6. write read array command. addresses(a) oe#(g) data(d/q) rp#(p) v ccw (v) ry/by#(r) (sr.7) a in a in t avav t aveh t ehax t ehgl t ehdx valid srd t phel t ehrl t vpeh t qvvl d in d in high z d in } } } } } } 1 2 3 4 5 6 v ih v il wp#(s) t sheh t qvsl v ih v il byte#(f) t fveh t ehfv v ih v il we#(w) t wlel t ehwh t ehqv1,2,3,4 t dveh v ih v il ce#(e) t ehel t eleh lhf80jt6 39 rev. 1.27 figure 19. ac waveform for ce#-controlled write operations
rp#(p) v il t plph t plrz v ih v ih high z ("1") v il v ol ("0") t plph ry/by#(r) (sr.7) rp#(p) v il t 2vph (c)rp# rising timing v ih 2.7v v il rp#(p) v cc (a)reset during read array mode (b)reset during block erase, full chip erase, word/byte write or lock-bit configuration high z ("1") v ol ("0") ry/by#(r) (sr.7) lhf80jt6 40 rev. 1.27 6.2.7 reset operations figure 20. ac waveform for reset operation reset ac specifications sym. parameter notes min. max. unit t plph rp# pulse low time 2 100 ns t plrz rp# low to reset during block erase, full chip erase, word/byte write or lock-bit configuration 1,2 30 s t 2vph v cc 2.7v to rp# high 2,3 100 ns notes: 1. if rp# is asserted while a block erase, full chip erase, word/byte write or lock-bit configuration operation is not executing , the reset will complete within 100ns. 2. a reset time, t phqv , is required from the later of ry/by#(sr.7) going high z("1") or rp# going high until outputs are valid. refer to ac characteristics - read-only operations for t phqv . 3. when the device power-up, holding rp# low minimum 100ns is required after v cc has been in predefined range and also has been in stable there.
lhf80jt6 41 rev. 1.27 6.2.8 block erase, full chip erase, word/byte write and lock-bit configuration performance (3) v cc =2.7v-3.6v, t a =-40c to +85c v ccw =2.7v-3.6v v ccw =11.7v-12.3v sym. parameter notes min. typ. (1) max. min. typ. (1) max. unit t whqv1 word write time 32k word block 2 33 200 20 s t ehqv1 4k word block 2 36 200 27 s byte write time 64k byte block 2 31 200 19 s 8k byte block 2 32 200 26 s block write time 32k word block 2 1.1 4 0.66 s (in word mode) 4k word block 2 0.15 0.5 0.12 s block write time 64k byte block 2 2.2 7 1.4 s (in byte mode) 8k byte block 2 0.3 1 0.25 s t whqv2 t ehqv2 block erase time 32k word block 64k byte block 2 1.2 6 0.9 s 4k word block 8k byte block 2 0.6 5 0.5 s full chip erase time 2 22.8 114 17.5 s t whqv3 t ehqv3 set lock-bit time 2 56 200 42 s t whqv4 t ehqv4 clear block lock-bits time 2 1 5 0.69 s t whrz1 t ehrz1 word/byte write suspend latency time to read 4 6 15 6 15 s t whrz2 t ehrz2 block erase suspend latency time to read 4 16 30 16 30 s t eres latency time from block erase resume command to block erase suspend command 5 600 600 s notes: 1. typical values measured at t a =+25c and v cc =3.0v, v ccw =3.0v or 12.0v. assumes corresponding lock-bits are not set. subject to change based on device characterization. 2. excludes system-level overhead. 3. sampled but not 100% tested. 4. a latency time is required from issuing suspend command(we# or ce# going high) until ry/by# going high z or sr.7 going "1". 5. if the time between writing the block erase resume command and writing the block erase suspend command is shorter than t eres and both commands are written repeatedly, a longer time is required than standard block erase until the completion of the operation.

rev. 1.10 i a-1 recommended operating conditions a-1.1 at device power-up ac timing illustrated in figure a-1 is recommended for the supply voltages and the control signals at device power-up. if the timing in the figure is ignored, the device may not operate correctly. figure a-1. ac timing at device power-up for the ac specifications t vr , t r , t f in the figure, refer to the next page. see the ?electrical specifications? described in specifications for the supply voltage range, the operating temperature and the ac specifications not shown in the next page. t 2vph *1 v cc gnd v cc (min) rp# v il v ih (p) t phqv v ccw *2 gnd v ccwh1/2 (v) ce# v il v ih (e) we# v il v ih (w) oe# v il v ih (g) wp# v il v ih (s) v oh v ol (d/q) data high z valid output t vr t f t r t elqv t f t glqv (a) address valid (rst#) (v pp ) t r or t f address v il v ih t avqv *1 t 5vph for the device in 5v operations. t r or t f t r t r *2 to prevent the unwanted writes, system designers should consider the v ccw (v pp ) switch, which connects v ccw (v pp ) to gnd during read operations and v ccwh1/2 (v pph1/2 ) during write or erase operations. (v pph1/2 ) see the application note ap-007-sw-e for details.
rev. 1.10 ii a-1.1.1 rise and fall time notes: 1. sampled, not 100% tested. 2. this specification is applied for not only the device power-up but also the normal operations. t r (max.) and t f (max.) for rp# (rst#) are 20 s/v. symbol parameter notes min. max. unit t vr v cc rise time 1 0.5 30000 s/v t r input signal rise time 1, 2 1 s/v t f input signal fall time 1, 2 1 s/v
rev. 1.10 iii a-1.2 glitch noises do not input the glitch noises which are below v ih (min.) or above v il (max.) on address, data, reset, and control signals, as shown in figure a-2 (b). the acceptable glitch noises are illustrated in figure a-2 (a). figure a-2. waveform for glitch noises see the ? dc characteristics ? described in specifications for v ih (min.) and v il (max.). (a) acceptable glitch noises input signal v ih (min.) input signal v ih (min.) input signal v il (max.) input signal v il (max.) (b) not acceptable glitch noises
rev. 1.10 iv a-2 related document information (1) note: 1. international customers should contact their local sharp or distribution sales office. document no. document name ap-001-sd-e flash memory family software drivers ap-006-pt-e data protection method of sharp flash memory ap-007-sw-e rp#, v pp electric potential switching circuit
s p e c i f i c a t i o n s a r e s u b j e c t t o c h a n g e w i t h o u t n o t i c e . s u g g e s t e d a p p l i c a t i o n s ( i f a n y ) a r e f o r s t a n d a r d u s e ; s e e i m p o r t a n t r e s t r i c t i o n s f o r l i m i t a t i o n s o n s p e c i a l a p p l i c a t i o n s . s e e l i m i t e d w a r r a n t y f o r s h a r p ? s p r o d u c t w a r r a n t y . t h e l i m i t e d w a r r a n t y i s i n l i e u , a n d e x c l u s i v e o f , a l l o t h e r w a r r a n t i e s , e x p r e s s o r i m p l i e d . a l l e x p r e s s a n d i m p l i e d w a r r a n t i e s , i n c l u d i n g t h e w a r r a n t i e s o f m e r c h a n t a b i l i t y , f i t n e s s f o r u s e a n d f i t n e s s f o r a p a r t i c u l a r p u r p o s e , a r e s p e c i f i c a l l y e x c l u d e d . i n n o e v e n t w i l l s h a r p b e l i a b l e , o r i n a n y w a y r e s p o n s i b l e , f o r a n y i n c i d e n t a l o r c o n s e q u e n t i a l e c o n o m i c o r p r o p e r t y d a m a g e . n o r t h a m e r i c a e u r o p e j a p a n s h a r p m i c r o e l e c t r o n i c s o f t h e a m e r i c a s 5 7 0 0 n w p a c i f i c r i m b l v d . c a m a s , w a 9 8 6 0 7 , u . s . a . p h o n e : ( 1 ) 3 6 0 - 8 3 4 - 2 5 0 0 f a x : ( 1 ) 3 6 0 - 8 3 4 - 8 9 0 3 f a s t i n f o : ( 1 ) 8 0 0 - 8 3 3 - 9 4 3 7 w w w . s h a r p s m a . c o m s h a r p m i c r o e l e c t r o n i c s e u r o p e d i v i s i o n o f s h a r p e l e c t r o n i c s ( e u r o p e ) g m b h s o n n i n s t r a s s e 3 2 0 0 9 7 h a m b u r g , g e r m a n y p h o n e : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 8 6 f a x : ( 4 9 ) 4 0 - 2 3 7 6 - 2 2 3 2 w w w . s h a r p s m e . c o m s h a r p c o r p o r a t i o n e l e c t r o n i c c o m p o n e n t s & d e v i c e s 2 2 - 2 2 n a g a i k e - c h o , a b e n o - k u o s a k a 5 4 5 - 8 5 2 2 , j a p a n p h o n e : ( 8 1 ) 6 - 6 6 2 1 - 1 2 2 1 f a x : ( 8 1 ) 6 1 1 7 - 7 2 5 3 0 0 / 6 1 1 7 - 7 2 5 3 0 1 w w w . s h a r p - w o r l d . c o m t a i w a n s i n g a p o r e k o r e a s h a r p e l e c t r o n i c c o m p o n e n t s ( t a i w a n ) c o r p o r a t i o n 8 f - a , n o . 1 6 , s e c . 4 , n a n k i n g e . r d . t a i p e i , t a i w a n , r e p u b l i c o f c h i n a p h o n e : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 4 1 f a x : ( 8 8 6 ) 2 - 2 5 7 7 - 7 3 2 6 / 2 - 2 5 7 7 - 7 3 2 8 s h a r p e l e c t r o n i c s ( s i n g a p o r e ) p t e . , l t d . 4 3 8 a , a l e x a n d r a r o a d , # 0 5 - 0 1 / 0 2 a l e x a n d r a t e c h n o p a r k , s i n g a p o r e 1 1 9 9 6 7 p h o n e : ( 6 5 ) 2 7 1 - 3 5 6 6 f a x : ( 6 5 ) 2 7 1 - 3 8 5 5 s h a r p e l e c t r o n i c c o m p o n e n t s ( k o r e a ) c o r p o r a t i o n r m 5 0 1 g e o s u n g b / d , 5 4 1 d o h w a - d o n g , m a p o - k u s e o u l 1 2 1 - 7 0 1 , k o r e a p h o n e : ( 8 2 ) 2 - 7 1 1 - 5 8 1 3 ~ 8 f a x : ( 8 2 ) 2 - 7 1 1 - 5 8 1 9 c h i n a h o n g k o n g s h a r p m i c r o e l e c t r o n i c s o f c h i n a ( s h a n g h a i ) c o . , l t d . 2 8 x i n j i n q i a o r o a d k i n g t o w e r 1 6 f p u d o n g s h a n g h a i , 2 0 1 2 0 6 p . r . c h i n a p h o n e : ( 8 6 ) 2 1 - 5 8 5 4 - 7 7 1 0 / 2 1 - 5 8 3 4 - 6 0 5 6 f a x : ( 8 6 ) 2 1 - 5 8 5 4 - 4 3 4 0 / 2 1 - 5 8 3 4 - 6 0 5 7 h e a d o f f i c e : n o . 3 6 0 , b a s h e n r o a d , x i n d e v e l o p m e n t b l d g . 2 2 w a i g a o q i a o f r e e t r a d e z o n e s h a n g h a i 2 0 0 1 3 1 p . r . c h i n a e m a i l : s m c @ c h i n a . g l o b a l . s h a r p . c o . j p s h a r p - r o x y ( h o n g k o n g ) l t d . 3 r d b u s i n e s s d i v i s i o n , 1 7 / f , a d m i r a l t y c e n t r e , t o w e r 1 1 8 h a r c o u r t r o a d , h o n g k o n g p h o n e : ( 8 5 2 ) 2 8 2 2 9 3 1 1 f a x : ( 8 5 2 ) 2 8 6 6 0 7 7 9 w w w . s h a r p . c o m . h k s h e n z h e n r e p r e s e n t a t i v e o f f i c e : r o o m 1 3 b 1 , t o w e r c , e l e c t r o n i c s s c i e n c e & t e c h n o l o g y b u i l d i n g s h e n n a n z h o n g r o a d s h e n z h e n , p . r . c h i n a p h o n e : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 1 f a x : ( 8 6 ) 7 5 5 - 3 2 7 3 7 3 5

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